This invention relates generally to the fabrication of semiconductor devices, and particularly to an advanced barrier film useful for forming single crystal metal in electronic devices.
Integrated circuits (ICs) are composed of vast number of active components such as transistors, resistors, and capacitors, and other active devices. These individual components are generally laid out in a two dimensional array on a substrate, such as silicon or gallium arsenide. The two dimensional arrays are often stacked on top of one another to form a three dimensional IC. As in any circuit, these components, and the several layers, must be connected to one another electrically. Interconnection on the two dimensional surfaces is accomplished by depositing lines or strips of metal that act as connecting xe2x80x9cwiresxe2x80x9d. Likewise, different levels of the metallization are interconnected vertically by metal plugs deposited in via holes made between the separate layers (levels). These steps in the manufacturing process are commonly referred to as xe2x80x9cmetallization,xe2x80x9d and are generally done as part of back-end-of-the-line processing.
Generally, silicon is the substrate material of choice, aluminum is the metal of choice for two dimensional IC metallization, and tungsten is the metal of choice for filling via holes for multiple layer interconnection. Silicon is preferred because it is cheap and abundant. Aluminum and tungsten are chosen because they have adequate electrical conductivity and they can be made not to diffuse into the substrate during the many annealing operations inherent in the IC manufacturing process.
However, because the electrical conductivity of aluminum and tungsten is limited, the lines and plugs must be made thick enough to ensure minimal resistance to electric current between components and between levels. The relative large size of these conductors has become an issue for IC designers and fabricators interested in placing a greater density of circuit elements on an IC. In order to achieve greater performance from ICs, the lateral dimensions of the circuit elements must be reduced. This reduction in IC element size has two detrimental effects on the resulting IC. First, it increases the resistance of the metal interconnects. Second, it increases the aspect ratio of the via holes, making them more difficult to fill with the metallic material. Incomplete filling of the via holes exacerbates the problem of high resistance. Today, there is often not enough space in the lateral direction on an IC chip to accommodate large aluminum conductors. Additionally, the size of the via holes, when filled with tungsten, limits the number of levels in the IC.
Copper has attracted widespread interest in the semiconductor processing field as an alternative metallization material. Because of copper""s greater electrical conductivity, copper conductors impose less resistance to the flow of electrons than aluminum or tungsten conductors having equivalent dimensions. In principle, smaller conductor lines should be feasible with copper to carry the same amount of current as aluminum or tungsten. Thus, the goal has been to achieve a tighter packing density per level, or reduce the number of metallization levels, using a copper interconnect strategy. Also, copper has superior resistance to poisoning due to electromigration from adjoining layers than aluminum, which also should make it a more reliable conductor. Therefore, copper has represented an attractive candidate for back-end-of-the line metallization, among other things.
However, a practical copper interconnect strategy for semiconductor devices has faced several problems. For instance, copper is susceptible to corrosion because it does not form a native self protective oxide surface film. Also, the electrochemical activity of copper is conducive to corrosion. As a consequence, adequate precautions are needed to protect the copper surface during polishing, cleaning and post-processing operations. However, as an even more notable problem of current interest, copper has a tendency to diffuse relatively easily at elevated temperatures into silicon. The copper which migrates into the silicon tends to produce deep-level defects, which can severely degrade the electrical characteristics of the devices. The probability of this problem arising is heightened due to the fact that ICs must be annealed several times during the fabrication process.
As efforts to impede the diffusion of copper into silicon and other adjacent materials, a variety of materials has already been proposed and used to form diffusion barriers and/or encapsulants for copper conductors. Previous copper barriers are described, for instance, in U.S. Pat. Nos. 5,151,168 (Gilton et al.), U.S. Pat. No. 5,695,810 (Dubin et al.), and U.S. Pat. No. 5,824,599 (Schacham-Diamand et al.). Currently, a special need exists for suitable barrier films for copper-filled damascene lines. That is, as known, copper is relatively difficult to etch so its implementation in interconnect schemes generally requires additive patterning, such as damascene patterning, in lieu of subtractive processing.
Among the barrier materials under development within the semiconductor industry, nitrides or silico-nitrides of the transition metals titanium, tantalum and tungsten (e.g., TiN, TaN, WN, TiWN, TiSiN, and TaSiN) are prevalently used. The thickness of the metal-nitride barrier layer required to stop copper diffusion into silicon effectively is in the range of tens to hundreds of nanometers, or hundreds to thousands of Angstroms (A). As shown in FIG. 2, which is based on published Semiconductor Industry Association data, presently achievable effective diffusion barrier thicknesses are generally in the 200-250 xc3x85 range for tantalum nitride, for example, although barrier film thicknesses for metallic copper that are smaller than that have been suggested in the prior art (e.g., see U.S. Pat. No. 5,824,599 to Schacham-Diamand et al.). A thick barrier layer can frustrate the advantage of using copper interconnects. Therefore, very thin barrier layers for copper are needed which still can maintain barrier efficacy even as the circuit feature sizes inexorably continue to shrink.
Another practical problem associated with implementing copper interconnects arises from the present state-of-the art wafer technology. Wafers for processing, ideally, would be atomically smooth, or equivalently have a perfect two-dimensional surface. This requirement typically is not completely met, i.e., it is not generally satisfied for the entire surface area of a standard 3 inch (7.6 cm) silicon wafer. In practice, microscopic steps and terraces of height more than one atomic layer usually exist and occur on any wafer that is manufactured from bulk crystals. In addition, the crystal orientation of the wafer generally is not perfect, as consequently there will be mis-oriented grains and grain boundaries that extend to the surface of the wafer. These imperfections on the wafer will tend to undermine conventional atomic diffusion barriers as they provide pathways for the diffusion of the copper atoms.
The problem of diffusion exists not only in the case of copper metallization on silicon, but also in the case of copper metallization on other single- and polycrystalline semiconductor substrate materials such as gallium arsenide, silicon carbide, germanium, and so forth. Also, copper diffusion or drift into insulating or dielectric materials, such as SiO2, can result in short circuits, especially in dense arrays of IC components. Diffusion is also a problem with other high conductivity metallization materials such as gold, silver, and platinum.
As can be appreciated from the foregoing, a barrier film is needed which is extremely thin, yet permits metallization using copper and other high conductivity metallic conductors which would otherwise have a tendency to diffuse into a substrate formed of a semiconducting material or an insulating material. It is further desired to improve electronic and electro-optic devices by making it possible to achieve one or more of the following desirable characteristics: increased component density in large scale integration, reduced heat dissipation, increased speed of operation, and a decreased number of metallization levels.
In accordance with this invention, an epitaxial barrier material provides not only a unique growth medium for growing single crystal structures of elemental metal thereon, but also provides an effective diffusion barrier at extremely thin thicknesses against migration of metal atoms from a conductor structure into an adjacent substrate. Moreover, the single crystal structures of the elemental metal are firmly attached to the barrier material to provide a stable and reliable metallization and/or contact scheme.
This invention is particularly advantageous for forming electrical conductor structures from single crystal, transition metals, in which the conductor structures can be layers, fines, filled trenches, contacts, bonding pads, and/or via plugs, and the like. For purposes of this invention, the xe2x80x9ctransition metalsxe2x80x9d are the elements of subgroups IIIB, IVB, VB, VIB, VIIB, VIII and IB in periods 4-7 of the Periodic Table (Long Period Form), and preferably those of subgroup IB of the Periodic Table (i.e., copper, silver, gold), as well as platinum. These metals are highly attractive for interconnect strategies on account of there intrinsic low resistivity and high reliability characteristics.
The present investigators have discovered that barrier materials meeting the purposes and objectives of this invention include certain epitaxial metal halides, which can behave as a solid state surfactant, i.e., a low surface energy material layer that xe2x80x9cwetsxe2x80x9d two materials that do not normally xe2x80x9cwetxe2x80x9d well. For instance, although the present investigators have observed that copper does not normally stick well to many insulators due to surface energy mismatches, among other things, the present invention embodies processing conditions that permits metal halides that can be epitaxially deposited, especially alkaline earth metal halides such as BaF2, to be transformed into solid state surfactants for purposes of growing single crystal elemental copper on the metal halide with tack strengths sustainable for metallization post-processing and service.
This invention is also significant because of its applicability to metals such as copper, which are especially prone to migration into and contamination of semiconductor substrates such as silicon upon moderate heating, as the epitaxial metal halide material serves as a diffusion barrier at relatively thin thicknesses to the single crystal metal structure formed in contact therewith.
In one embodiment of this invention, a semiconductor device is fabricated by providing a heteroepitaxial barrier film derived from a suitable metal halide as described herein on a surface of a substrate material, and a metallic conductor having a tendency to diffuse into the substrate material is formed on the barrier film, in which the metallic conductor has a single crystal structure.
In one preferred method of this invention, the procedure involves the formation of a heteroepitaxial (xe2x80x9ccompositexe2x80x9d) barrier film and single crystal metal structure, in that order, on a substrate surface through a three-stage operation. In a first stage, a monolayer portion of the barrier material is first produced on the substrate surface by depositing a continuous coating of metal halide upon a clean, hot surface of a semiconducting substrate material under ultrahigh vacuum conditions of less than 10xe2x88x9211 Torr chamber background pressure, and then the metal halide vapor is discontinued while the coated substrate is heated for a time period such that the metal halide first reacts with the substrate material and dissociates. This forms an uncontaminated metal/substrate surface reaction product while releasing gaseous by-products formed of substrate atoms and halogen atoms of the metal halide compound. This surface reaction is self-limiting as it forms a monolayer of metal atoms derived from the metal halide that are tightly attached to the substrate surface as part of a uniform epitaxial surface reaction product. In a second stage, the vapor deposition of metal halide then is resumed under the ultra high vacuum conditions so that a single crystal homoepitaxial film portion of the barrier material, which is formed of the metal halide molecules of the desired thickness, is formed upon the monolayer portion of the barrier material. The monolayer (monoatomic) layer of metal atoms and the homoepitaxial film of metal halide together provide a heteroepitaxial, composite barrier film. Then, in a third stage of the procedure, a metal is deposited upon the heteroepitaxial barrier film, and the surface of the barrier film that is heated either during the metal deposition or as a post-deposition anneal procedure to form a high quality, single crystal structure of metal directly on the barrier film. The heteroepitaxial barrier film can be formed in uniform thicknesses as small as several hundred angstroms thick, and preferably 100 xc3x85 or less, and even 75 xc3x85 or less, to provide extremely thin barrier film thicknesses for copper and similarly behaving metals in semiconductor device contexts. Among other things, these very thin, yet effective diffusion barrier thicknesses achieved by this invention supports tighter packing density objectives.
The metal halide compound used in forming the heteroepitaxial barrier film in the practice of this invention preferably behaves as a solid state surfactant described herein during metal deposition. Useful metal halides in this regard include bariurn, strontium, or cesium- halide salts that can be vapor deposited on a substrate. As indicated above, the elemental metal that can be deposited in the single crystal form on the metal halide barrier films formed by this invention are not particularly limited, but advantageously include metals which readily diffuse into silicon at moderately high temperatures such as copper, silver, gold, and platinum, singly or in combinations thereof.
Another advantage of the present invention, is that the heteroepitaxial barrier film conforms well to the surface contour of a substrate, whether the surface contour is very smooth or uneven, without leaving bare (uncoated) spots on the substrate surface, which increases the versatility of the invention. That is, the diffusion barrier layer of this invention can be implemented on not only semiconductor and electro-optic materials that have two-dimensional single crystalline surfaces, but it also has wider applicability encompassing substrate surfaces that contain crystalline defects (e.g., pits, crystalline mis-orientations, and steps). Further, the diffusion barrier layer also blocks the diffusion pathways on imperfect crystalline surfaces, and hence will be of more practical and immediate applicability with imperfect wafer surfaces, and hence the existing wafer technology. Also, in the case bulk metal halide crystals, the metal can be deposited directly on the crystal and processed according to this invention.
An important advantage of this invention is that a copper conductor can be formed on a very thin, yet effective, diffusion barrier film as a highly organized, single crystal (monocrystalline) structure. The single crystal morphology of the deposited copper yields even lower resistivity characteristics, as compared to polycrystalline forms of the metal, permitting even thinner interconnect lines. Consequently, the copper lines formed by this invention provide superior conductivity characteristics, permitting further line size reductions.
Furthermore, as the thickness of polycrystalline metal film gets smaller (e.g. on the order of approximately 400 xc3x85 or less), there is a general increase in its resistivity. This is because the conducting electrons are now scattered by the boundaries of the metal film. This is alleviated in the present invention by providing the metal film in a single crystalline morphology, in which case the electrons are scattered specularly at the surface. That is, even if the electrons are scattered, their energy and momentum are conserved because of the near-perfect atomic arrangement of the single crystalline film surface created by the present invention. Hence there is only minimal increase in the resistivity of the metal with a decrease in film thickness. Various other objects, details and advantages of the invention will be apparent from the following detailed description when read in conjunction with the drawings.